{"version":"1.0","provider_name":"GO 2 UVM - for VLSI Designers","provider_url":"http:\/\/www.go2uvm.org","author_name":"UnleashingUVM","author_url":"http:\/\/www.go2uvm.org\/author\/g2uroot\/","title":"Handling variable delays in SystemVerilog Assertions","type":"rich","width":600,"height":338,"html":"
Handling variable delays in SystemVerilog Assertions<\/a><\/blockquote>\n