For those using UVM in live projects and looking to see what’s next in DV – here is an opportunity to learn (for free) UVM Registers -a definitive first step to “Portable Stimulus”. Accellera’s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next big wave in DV space.
CVC, a global leader in VLSI Design-Verification training is pleased to offer a free half-a-day training on UVM RAL/Registers. It is free of cost, but registration is must.
Register at: https://goo.gl/forms/2UQvmI90Lp6dgKwk2
When? Dec 17th, 2016 Saturday, 10 AM – 1 PM (Indian Standard Time)
Address: http://www.fb.com/cvc.uvm/about
Cost: FREE
All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http://verifnews.org/publications/books/
Hurry, limited seating, first-come-first-serve basis.
Agenda:
• UVM introduction
• Capturing registers in UVM
• Using XL sheet to capture Register Specification
• Brief look at IP-XACT for register specification
• Case studies: popular IPs and their register specifications
• Demo: VerifWorks DVCreate PSS tool to generate UVM-RAL model from IP-XACT
Register via: https://goo.gl/forms/2UQvmI90Lp6dgKwk2