For those using UVM in live projects and looking to see what\u2019s next in DV \u2013 here is an opportunity to learn (for free) UVM Registers -a definitive first step to \u201cPortable Stimulus\u201d. Accellera\u2019s PSS working group is working on defining how a portable test specification can be defined and is expected to be the next big wave in DV space.<\/p>\n\n\n\n
CVC, a global leader in VLSI Design-Verification training is pleased to offer a free half-a-day training on UVM RAL\/Registers. It is free of cost, but registration is must.<\/p>\n\n\n\n
Register at: <\/strong>https:\/\/goo.gl\/forms\/2UQvmI90Lp6dgKwk2<\/a><\/p>\n\n\n\n When? <\/strong>Dec 17th, 2016 Saturday, 10 AM \u2013 1 PM (Indian Standard Time)<\/p>\n\n\n\n Address:<\/strong> http:\/\/www.fb.com\/cvc.uvm\/about <\/a><\/p>\n\n\n\n Cost: FREE<\/strong><\/p>\n\n\n\n All Attendees will have the option of buying the best selling SVA book at 10% discount, see: http:\/\/verifnews.org\/publications\/books\/<\/a> <\/a><\/p>\n\n\n\n Hurry, limited seating, first-come-first-serve basis.<\/p>\n\n\n\n Agenda:<\/strong><\/p>\n\n\n\n \u2022 UVM introduction<\/p>\n\n\n\n \u2022 Capturing registers in UVM<\/p>\n\n\n\n \u2022 Using XL sheet to capture Register Specification<\/p>\n\n\n\n \u2022 Brief look at IP-XACT for register specification<\/p>\n\n\n\n \u2022 Case studies: popular IPs and their register specifications<\/p>\n\n\n\n \u2022 Demo: VerifWorks DVCreate PSS tool to generate UVM-RAL model from IP-XACT<\/p>\n\n\n\n