Debug UVM factory with these great tips!

Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides a means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts, and best practices.

Given the major adoption of UVM across the globe and the industry, advanced users are looking for tips and tricks to improve their productivity. UVM does define a structured framework for building complex testbenches. It is built on strong OOP principles and design patterns using underlying SystemVerilog language features. This strong OOP nature presents certain challenges to the end users. Recall that many Design-Verification (DV) engineers come from hardware, and electronics backgrounds and not heavy Software backgrounds. Hence at times, it gets tricky for users to debug UVM-based testbenches when things do not work as expected.

In this article, the authors share their long experience of assisting customers with run-time debugging of common UVM issues and potential solutions to them. During our various training and consulting engagements using UVM, we have seen DV engineers struggling to debug relatively simple UVM issues. It will be unfair to blame the users as many a time, the error messages are cryptic and do not point to the actual source code, but rather somewhere from the base classes, making the debugging difficult. We have captured a series of such common issues and error messages into a collateral form that we call “UVM Vault”. As part of our QVP engagement with Mentor Graphics, we are integrating this UVM Vault to Questa® soon

Originally published in Verification Horizons – June 2016 | Volume 12, Issue 2

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